1. Technical Field
The present disclosure relates to a display device, and more particularly, to a skew adjustment circuit and a method of adjusting skew.
2. Discussion of the Related Art
Display devices may include STN (super-twisted nematic) LCD (liquid crystal display) panel or a TFT (thin film transistor) LCD panel and a driving circuit driving the LCD panel. In the case of a TFT-LCD, the driving circuit includes a gate driver driving gate lines of a TFT, a source driver driving source lines of the TFT, and a timing controller. As the gate driver turns on the TFT by applying a high voltage, and the source driver applies source driving signals to the source lines for displaying colors, a screen is displayed on the TFT-LCD.
A timing controller controls the gate driver and the source driver based on display control signals such as a clock signal, a display timing signal, a horizontal synchronization signal, a vertical synchronization signal, etc. and display data (R, G, and B). The timing controller transmits output display data, an output clock signal, an output start pulse signal, etc. to signal lines of a source driver and transmission lines between source drivers. To help the source driver accurately receive output display data, the timing controller may adjust the skew of the output clock signals using a DLL (delay locked loop) circuit.
A delay-locked loop (DLL) is a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal oscillator. A DLL can be used to change the phase of a clock signal, usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits.
FIG. 1 illustrates a conventional skew adjustment circuit 100. Referring to FIG. 1, the skew adjustment circuit 100 includes a DLL circuit 110 and a D-flipflop 120. The DLL circuit 110 responds to a skew control signal DLL_SKEW to delay an input clock signal CLK_IN by a skew value and then generates an output clock signal CLK_OUT. The D-flipflop 120 responds to the output clock signal CLK_OUT to receive an input start pulse signal STH_IN and output an output start pulse signal STH_OUT. The skew adjustment circuit 100 outputs the output clock signal CLK_OUT and the output start pulse signal STH_OUT which are delayed by the skew value.
FIG. 2 is a timing diagram of the skew adjustment circuit 100 of FIG. 1. Referring to FIG. 2, an output clock signal CLK_OUT is delayed by a ⅛ period of an input clock signal CLK_IN according to a skew control signal DLL_SKEW. That is, if a skew value of the skew control signal DLL_SKEW is 0, the output clock signal CLK_OUT is generated according to the input clock signal CLK_IN. If a skew value of the skew control signal DLL_SKEW is 1, the output clock signal CLK_OUT delayed by a ⅛ period of the input clock signal CLK_IN is generated, and an output start pulse signal STH_OUT delayed by a ⅛ period of the input clock signal CLK_IN is generated from an input start pulse signal STH_IN. In the same manner, when a skew value of the skew control signal DLL_SKEW is 2 or 3, the output clock signal CLK_OUT delayed by a 2/8 or ⅜ period of the input clock signal CLK_IN is generated from the input clock signal CLK_IN, and an output start pulse signal STH_OUT delayed by a 2/8 or ⅜ period of the input clock signal CLK_IN is generated from an input start pulse signal STH_IN.
However, if a skew value of the skew control signal DLL_SKEW is 4 or greater, a delay effect of the output clock signal CLK_OUT and the output start pulse signal STH_OUT cannot be obtained from the skew adjustment circuit 100.
Accordingly there exists a need for skew adjustment circuit and method that can obtain an accurate delay effect.